1. Field of the Invention
This invention relates to the field of converting digital signals to analog representation and, more particularly, to high resolution pipelined digital-to-analog converters.
2. Description of Related Art
A wide variety of analog devices are often controlled by digital computers, examples of which include various types of analog positioning devices which may be part of systems designed to control missile steerage and speed. To interface these devices with digital computers, circuits known as digital-to-analog converters have been developed which can provide an analog output voltage dependent on the value of a digital input signal from the computer. The output voltage of an n-bit digital-to-analog converter can typically be represented as: EQU V.sub.out =V.sub.ref (b.sub.o.sup.2.spsp.-n- +b.sub.1.sup.2.spsp.-(n-1) +b.sub.2.sup.2.spsp.-(n-2) + . . . +b.sub.n-1.sup.2.spsp.-1)
where V.sub.out is the output voltage of the converter, V.sub.ref is a reference voltage applied to the converter, and b.sub.o -b.sub.1. . . -b.sub.n-1 is the digital input signal delivered to the converter where b.sub.o represents the least significant bit and b.sub.n-1 is the most significant bit.
Many digital-to-analog converters are essentially voltage divider networks having each bit driving a weighted resistor to produce the desired output voltage. Other digital-to-analog converters use an R-2R resistive ladder, in which resistors of two values are arranged in a ladder network to produce an analog output signal. Because resistors fabricated from polysilicon or by diffusion are inherently large and non-linear with respect to voltage, the preferred practice in MOS (metal oxide semiconductor) technology is to use capacitive elements in integrated digital-to-analog converters. Such capacitors are typically constructed by placing a metal or polysilicon electrode over a thin insulating layer on the surface of a doped region of the silicon substrate or on the surface of a second polysilicon layer. By using binary weighted conversion capacitors and fedback capacitors of this type, in conjunction with field-effect transistors, digital-to-analog converters can be fabricated relatively simply.
While digital-to-analog converters using binary weighted capacitors can be fabricated using MOS technology as described above, their utility often becomes limited as the desired resolution (i.e., the number of bits to be converted) increases. Since each bit generally requires a weighted conversion capacitor having a value equal to twice that of the next least significant bit, the ratio of the feedback capacitance to that of the conversion capacitor associated with the least significant bit doubles for each one bit increase in resolution. This doubling of the capacitance ratio may inherently reduce the accuracy of conversion by a statistically determined quantity and has generally limited resolution of MOS converters to approximately 8 bits in actual practice.
In addition, the digital-to-analog converters fabricated using MOS are not generally pipelined (i.e., unable to operate on more than one word simultaneously) thus limiting throughput. Though relatively fast converters exist in other technologies, a number of difficulties have emerged in attempting to implement pipelined converters using MOS fabrication techniques. In addition to requiring resistors having the disadvantages described above, the energy dissipated by these converters is generally relatively large and hence, unsuitable for MOS implementation.